| Mnemonic | Encoding | Description |
|---|---|---|
| BK0 | 0000 | MSR2[12] |
| BK1 | 0001 | MSR2[13] |
| BK2 | 0010 | MSR2[14] |
| BK3 | 0011 | MSR2[15] |
| ME0 | 0100 | MSR0[12] |
| ME1 | 0101 | MSR0[13] |
| ME2 | 0110 | MSR0[14] |
| ME3 | 0111 | MSR0[15] |
| OPM | 1000 | MSR1[3] |
| OPMA | 1001 | MSR1[7] |
| OP | 1010 | MSR0[9] |
| USM | 1011 | MSR1[4] |
| MV | 1100 | MSR1[2] |
| XSD | 1101 | MSR0[10] |
| PSH1 | 1110 | MSR1[5] |
| NQ | 1111 | MSR1[6] |
| # | Instruction | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | ECLD | 0 | 0 | 0 | 0 | imm:5 | LS | Dn | |||||||
| 1 | ELD mg,#imm:16 | 0 | 0 | 0 | 1 | 0 | mg | imm:3 | |||||||
| 2 | EMOD0 An,#imm:16 | 0 | 0 | 0 | 1 | 1 | 0 | mod0 | An | imm:3 | |||||
| 3 | ELD mgx,#imm:16 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | mgx | imm:3 | ||||
| 4 | ERPN rpi, #imm:16 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | rpi | imm:3 | ||||
| 5 | ELD An,adr:16 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | An | adr:3 | ||||
| 6 | ELD adr:16,An | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | An | adr:3 | ||||
| 7 | EMAD Mi, XiYi, mgx,@rps | 0 | 0 | 1 | 0 | XiYi | mgx | 0 | Mi | rps | |||||
| 8 | EMSB Mi, XiYi, mgx,@rps | 0 | 0 | 1 | 0 | XiYi | mgx | 1 | Mi | rps | |||||
| 9 | EMLD Mi, XiYi, mgx,@rps | 0 | 0 | 1 | 1 | XiYi | mgx | 0 | Mi | rps | |||||
| 10 | EMUL XiYi, mgx,@rps | 0 | 0 | 1 | 1 | XiYi | mgx | 1 | 0 | rps | |||||
| 11 | EADD Mi,P, mgx,@rps | 0 | 0 | 1 | 1 | 0 | Mi | mgx | 1 | 1 | rps | ||||
| 12 | ESUB Mi,P, mgx,@rps | 0 | 0 | 1 | 1 | 1 | Mi | mgx | 1 | 1 | rps | ||||
| 13 | EADD Mi,P, An,@rps | 0 | 1 | 0 | 0 | 0 | Mi | An | 0 | 0 | rps | ||||
| 14 | ESUB Mi,P, An,@rps | 0 | 1 | 0 | 0 | 0 | Mi | An | 0 | 1 | rps | ||||
| 15 | ELD Mi,P, An,@rps | 0 | 1 | 0 | 0 | 0 | Mi | An | 1 | 0 | rps | ||||
| 16 | ELD Mi,P, mgx,@rps | 0 | 1 | 0 | 0 | 0 | Mi | mgx | 1 | 1 | rps | ||||
| 17 | EADD Mi,P, @rpd,mga | 0 | 1 | 0 | 0 | 1 | Mi | mga | 0 | 0 | rpd | ||||
| 18 | ESUB Mi,P, @rpd,mga | 0 | 1 | 0 | 0 | 1 | Mi | mga | 0 | 1 | rpd | ||||
| 19 | ELD Mi,P, @rpd,mga | 0 | 1 | 0 | 0 | 1 | Mi | mga | 1 | 0 | rpd | ||||
| 20 | EADD Mi,P, @rpd,P | 0 | 1 | 0 | 0 | 1 | Mi | 0 | 0 | 1 | 1 | rpd | |||
| 21 | ESUB Mi,P, @rpd,P | 0 | 1 | 0 | 0 | 1 | Mi | 0 | 1 | 1 | 1 | rpd | |||
| 22 | ELD Mi,P, @rpd,P | 0 | 1 | 0 | 0 | 1 | Mi | 1 | 0 | 1 | 1 | rpd | |||
| 23 | reserved | 0 | 1 | 0 | 0 | 1 | d | 1 | 1 | 1 | 1 | d | d | d | |
| 24 | EADD Ai,Mi, mgx,@rps | 0 | 1 | 0 | 1 | 0 | Mi | mgx | 0 | Ai | rps | ||||
| 25 | ESUB Ai,Mi, mgx,@rps | 0 | 1 | 0 | 1 | 0 | Mi | mgx | 1 | Ai | rps | ||||
| 26 | ELD Ai,Mi, mgx,@rps | 0 | 1 | 0 | 1 | 1 | Mi | mgx | 0 | Ai | rps | ||||
| 27 | EADD Ai,Mi, Mi,@rps | 0 | 1 | 0 | 1 | 1 | Mi | 0 | 0 | 1 | Ai | rps | |||
| 28 | ESUB Ai,Mi, Mi,@rps | 0 | 1 | 0 | 1 | 1 | Mi | 0 | 1 | 1 | Ai | rps | |||
| 29 | ELD Ai,Mi, Mi,@rps | 0 | 1 | 0 | 1 | 1 | Mi | 1 | 0 | 1 | Ai | rps | |||
| 20 | ELD Pi,@rps | 0 | 1 | 0 | 1 | 1 | Pi | 1 | 1 | 1 | 0 | rps | |||
| 31 | reserved | 0 | 1 | 0 | 1 | 1 | d | 1 | 1 | 1 | 1 | d | d | d | |
| 32 | EADD Ai,Mi, @rpd,mga | 0 | 1 | 1 | 0 | 0 | Mi | mga | 0 | Ai | rpd | ||||
| 33 | ESUB Ai,Mi, @rpd,mga | 0 | 1 | 1 | 0 | 0 | Mi | mga | 1 | Ai | rpd | ||||
| 34 | ELD Ai,Mi, @rpd,mga | 0 | 1 | 1 | 0 | 1 | Mi | mga | 0 | Ai | rpd | ||||
| 35 | EADD Ai,Mi, @rpd,P | 0 | 1 | 1 | 0 | 1 | Mi | 0 | 0 | 1 | Ai | rpd | |||
| 36 | ESUB Ai,Mi, @rpd,P | 0 | 1 | 1 | 0 | 1 | Mi | 0 | 1 | 1 | Ai | rpd | |||
| 37 | ELD Ai,Mi, @rpd,P | 0 | 1 | 1 | 0 | 1 | Mi | 1 | 0 | 1 | Ai | rpd | |||
| 38 | ELD @rpd,P | 0 | 1 | 1 | 0 | 1 | Pi | 1 | 1 | 1 | 0 | rpd | |||
| 39 | reserved | 0 | 1 | 1 | 0 | 1 | d | 1 | 1 | 1 | 1 | d | d | d | |
| 40 | EADD Ai,Ci, Cj,@rps | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Ci | Cj | Ai | rps | |||
| 41 | ESUB Ai,Ci, Cj,@rps | 0 | 1 | 1 | 1 | 0 | 0 | 1 | Ci | Cj | Ai | rps | |||
| 42 | ELD Ai,Ci, Cj,@rps | 0 | 1 | 1 | 1 | 0 | 1 | 0 | Ci | Cj | Ai | rps | |||
| 43 | EMAX Ai,Ci, Ci,@rps | 0 | 1 | 1 | 1 | 0 | 1 | 1 | Ci | 0 | Ai | rps | |||
| 44 | EMIN Ai,Ci, Ci,@rps | 0 | 1 | 1 | 1 | 0 | 1 | 1 | Ci | 1 | Ai | rps | |||
| 45 | ELD mg1,@rps | 0 | 1 | 1 | 1 | 1 | mg1 | 0 | 0 | rps | |||||
| 46 | ELD An,@rps | 0 | 1 | 1 | 1 | 1 | 0 | An | 0 | 1 | rps | ||||
| 47 | ELD srg,@rps | 0 | 1 | 1 | 1 | 1 | 1 | srg | 0 | 1 | rps | ||||
| 48 | ELD @rpd,mg1 | 0 | 1 | 1 | 1 | 1 | mg1 | 1 | 0 | rpd | |||||
| 49 | ELD @rpd,An | 0 | 1 | 1 | 1 | 1 | 0 | An | 1 | 1 | rpd | ||||
| 50 | ELD @rps,srg | 0 | 1 | 1 | 1 | 1 | 1 | srg | 1 | 1 | rpd | ||||
| 51 | EMAD Mi, XiYi, Xi,@rp01s, Yi,@rp3s | 1 | 0 | 0 | 0 | XiYi | Xi | Yi | 0 | Mi | rp3 | rp01s | |||
| 52 | EMSB Mi, XiYi, Xi,@rp01s, Yi,@rp3s | 1 | 0 | 0 | 0 | XiYi | Xi | Yi | 1 | Mi | rp3 | rp01s | |||
| 53 | EMLD Mi, XiYi, Xi,@rp01s, Yi,@rp3s | 1 | 0 | 0 | 1 | XiYi | Xi | Yi | 0 | Mi | rp3 | rp01s | |||
| 54 | EMUL XiYi, Xi,@rp01s, Yi,@rp3s | 1 | 0 | 0 | 1 | XiYi | Xi | Yi | 1 | 0 | rp3 | rp01s | |||
| 55 | ELD Xi,@rp01s, Yi,@rp3s | 1 | 0 | 0 | 1 | 0 | 0 | Xi | Yi | 1 | 1 | rp3 | rp01s | ||
| 56 | reserved | 1 | 0 | 0 | 1 | 0 | 1 | d | d | 1 | 1 | d | d | d | |
| 57 | reserved | 1 | 0 | 0 | 1 | 1 | d | d | d | 1 | 1 | d | d | d | |
| 58 | ESFT asr,asa | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | asr | asa | |||
| 59 | ESFTA asr,asa | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | asr | asa | |||
| 60 | ESFTL asr,asa | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | asr | asa | |||
| 61 | ESFTD asr,asa | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | asr | asa | |||
| 62 | ELD SA,#imm:5 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | imm:5 | |||||
| 63 | ENMSK SG,#imm:4 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | imm:4 | ||||
| 64 | ELD srgd,srgd | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | srgs | srg | |||
| 65 | ELD rpui,rpd1.adr:2 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | adr:2 | rpui | |||||
| 66 | ELD rpd1.adr:2,rpui | 1 | 0 | 1 | 0 | 0 | 1 | 1 | adr:2 | rpui | |||||
| 67 | ESD0 ns,#imm:4 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | ns | imm:4 | |||||
| 68 | ESD1 ns,#imm:4 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | ns | imm:4 | |||||
| 69 | ESD2 ns,#imm:4 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | ns | imm:4 | |||||
| 70 | ESD3 ns,#imm:4 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | ns | imm:4 | |||||
| 71 | ELD An,rpdi.adr:5 | 1 | 0 | 1 | 1 | 0 | rpd | An | adr:5 | ||||||
| 72 | ELD rpdi.adr:5,An | 1 | 0 | 1 | 1 | 1 | rpd | An | adr:5 | ||||||
| 73 | EMOD0 An,mg | 1 | 1 | 0 | 0 | mod0 | An | mg | |||||||
| 74 | EMOD0 An,Am | 1 | 1 | 0 | 1 | 0 | 0 | An | 0 | mod0 | Am | ||||
| 75 | EMOD0 An,mgx | 1 | 1 | 0 | 1 | 0 | 0 | An | 1 | mod0 | mgx | ||||
| 76 | ELD mg,An | 1 | 1 | 0 | 1 | 0 | 1 | An | mg | ||||||
| 77 | EMAD Mi, XiYi, Ai,Mj | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | Mi | Ai | Mj | XiYi | ||
| 78 | EMSB Mi, XiYi, Ai,Mj | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | Mi | Ai | Mj | XiYi | ||
| 79 | EMLD Mi, XiYi, Ai,Mj | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | Mi | Ai | Mj | XiYi | ||
| 80 | EMUL XiYi, Ai,Mj | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | Ai | Mj | XiYi | ||
| 81 | EMAX Ai,Ci | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | Ai | Ci | 0 | 0 | |
| 82 | EMIN Ai,Ci | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | Ai | Ci | 0 | 1 | |
| 83 | EMAX Ai,Ai’ | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | Ai | 0 | 1 | 0 | |
| 84 | EMIN Ai,Ai’ | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | Ai | 0 | 1 | 1 | |
| 85 | NOP | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | d | 1 | 1 | d | |
| 86 | ELD mg1d,mg1s | 1 | 1 | 0 | 1 | 1 | 1 | 0 | mg1s | mg1d | |||||
| 87 | ELD mg2d,mg2s | 1 | 1 | 0 | 1 | 1 | 1 | 1 | mg2s | mg2d | |||||
| 88 | EMAD Mi, XiYi, Ai,MjSL | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | Mi | Ai | Mj | XiYi | ||
| 89 | EMSB Mi, XiYi, Ai,MjSL | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | Mi | Ai | Mj | XiYi | ||
| 90 | EMLD Mi, XiYi, Ai,MjSL | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | Mi | Ai | Mj | XiYi | ||
| 91 | EMUL XiYi, Ai,MjSL | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | Ai | Mj | XiYi | ||
| 92 | EMAD Mi, XiYi | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Mi | XiYi | ||
| 93 | EMSB Mi, XiYi | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Mi | XiYi | ||
| 94 | EMAD Mi, XiYi, Ai,MjSR | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | Mi | Ai | Mj | XiYi | ||
| 95 | EMSB Mi, XiYi, Ai,MjSR | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | Mi | Ai | Mj | XiYi | ||
| 96 | EMLD Mi, XiYi, Ai,MjSR | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | Mi | Ai | Mj | XiYi | ||
| 97 | EMUL XiYi, Ai,MjSR | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | Ai | Mj | XiYi | ||
| 98 | EMLD Mi, XiYi | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | Mi | XiYi | ||
| 99 | EMUL XiYi | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | XiYi | ||
| 100 | ERPR rpi | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | rpi | ||
| 101 | ELD An,#imm:5 | 1 | 1 | 1 | 0 | 1 | 0 | An | imm:5 | ||||||
| 102 | EADD An,#imm:5 | 1 | 1 | 1 | 0 | 1 | 1 | An | imm:5 | ||||||
| 103 | ECP An,#imm:5 | 1 | 1 | 1 | 1 | 0 | 0 | An | imm:5 | ||||||
| 104 | EMOD1 An | 1 | 1 | 1 | 1 | 0 | 1 | An | T | mod1 | |||||
| 105 | ERPN rpi,An | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | An | rpi | |||
| 106 | ERPS rps | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | rps | |||
| 107 | ERPD rpd | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | rpd | |||
| 108 | EMOD2 Mi | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | Mi | mod2 | ||||
| 109 | ETST cc T/EC3 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | TE | cc | ||||
| 100 | ER/ES bs | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | ES | bs | ||||
| 111 | ELD Pi,mg1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | Pi | mg1 | |||
| 112 | ELD mg1,Pi | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | Pi | mg1 | |||
| 113 | ELD mgx,An | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | An | mgx | |||
| 114 | ELD sdid,sdis | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | sdis | sdid | |||
| 115 | EBK #imm:4 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | imm:4 | ||||
| 116 | ESEC0 #imm:4 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | imm:4 | ||||
| 117 | ESEC1 #imm:4 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | imm:4 | ||||
| 118 | ESEC2 #imm:4 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | imm:4 | ||||
MSR0.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ME3 ME2 ME1 ME0 XSD OP VS V N Z C T
MSR1.
15 14 13 12 11 8 7 4 3 0 BK3 BK2 BK1 BK0 SEC2 SEC1 SEC0
· rps
Mnemonic Encoding Description
RP0+S0 000 RP0 post-modified by SD0 S0 field
RP1+S0 001 RP1 post-modified by SD1 S0 field
RP2+S0 010 RP2 post-modified by SD2 S0 field
RP3+S0 011 RP3 post-modified by SD3 S0 field
RP0+S1 100 RP0 post-modified by SD0 S1 field
RP1+S1 101 RP1 post-modified by SD1 S1 field
RP2+S1 110 RP2 post-modified by SD2 S1 field
RP3+S1 111 RP3 post-modified by SD3 S1 field
· rpd
Mnemonic Encoding Description
RP0+D0 000 RP0 post-modified by SD0 D0 field
RP1+D0 001 RP1 post-modified by SD1 D0 field
RP2+D0 010 RP2 post-modified by SD2 D0 field
RP3+D0 011 RP3 post-modified by SD3 D0 field
RP0+D1 100 RP0 post-modified by SD0 D1 field
RP1+D1 101 RP1 post-modified by SD1 D1 field
RP2+D1 110 RP2 post-modified by SD2 D1 field
RP3+D1 111 RP3 post-modified by SD3 D1 field
· rp01s
Mnemonic Encoding Description
RP0+S0 00 RP0 post-modified by SD0 S0 field
RP1+S0 01 RP1 post-modified by SD1 S0 field
RP0+S1 10 RP0 post-modified by SD0 S1 field
RP1+S1 11 RP1 post-modified by SD1 S1
· rp3s
Mnemonic Encoding Description
RP3+S0 0 RP3 post-modified by SD3 S0 field
RP3+S1 1 RP3 post-modified by SD3 S1 field
· mg1
Mnemonic Encoding Description
Y0 000 Y0[23:0] register
Y1 001 Y1[23:0] register
X0 010 X0[23:0] register
X1 011 X1[23:0] register
MA0(H) 100 MA0[51:0] / MA0[47:24] register
MA0L 101 MA0[23:0] register
MA1(H) 110 MA1[51:0] / MA1[47:24] register
MA1L 111 MA1[23:0] register
· mg2
Mnemonic Encoding Description
RP0 000 current bank RP0[15:0] register
RP1 001 current bank RP1[15:0] register
RP2 010 current bank RP2[15:0] register
RP3 011 current bank RP3[15:0] register
RPD0 100 RPD0[15:0] register
RPD1 101 RPD1[15:0] register
MC0 110 MC0[15:0] register
MC1 111 MC1[15:0]
· sdi
Mnemonic Encoding Description
SD0 00 current bank SD0[15:0] register (SD0 or SD0E)
SD1 01 current bank SD1[15:0] register
SD2 10 current bank SD2[15:0] register
SD3 11 current bank SD3[15:0] register (SD3 or SD3E)
· Ai
Mnemonic Encoding Description
A 0 A[23:0] register
B 1 B[23:0] register
· Ci
Mnemonic Encoding Description
C 0 C[23:0] register
D 1 D[23:0] register
· An
Mnemonic Encoding Description
A 00 A[23:0] register
B 01 B[23:0] register
C 10 C[23:0] register
D 11 D[23:0]
(1) Abbreviation Definition and Encoding (Continued) · rpui
Mnemonic Encoding Description
RP0 0000 current bank RP0[15:0] register
RP1 0001 current bank RP1[15:0] register
RP2 0010 current bank RP2[15:0] register
RP3 0011 current bank RP3[15:0] register
MC0_0 0100 MC0[15:0] register (set 0)
MC1_0 0101 MC1[15:0] register (set 0)
MC0_1 0110 MC0[15:0] register (set 1)
MC1_1 0111 MC1[15:0] register (set 1)
SD0_0 1000 current bank SD0[15:0] register (set 0)
SD1_0 1001 current bank SD1[15:0] register (set 0)
SD2_0 1010 current bank SD2[15:0] register (set 0)
SD3_0 1011 current bank SD3[15:0] register (set 0)
SD0_1 1100 current bank SD0[15:0] register (set 1)
SD1_1 1101 current bank SD1[15:0] register (set 1)
SD2_1 1110 current bank SD2[15:0] register (set 1)
SD2_1 1111 current bank SD3[15:0] register (set 1)
· mga
Mnemonic Encoding Description
MA0 00 MA0[51:0] / MA0[47:24] register
MA1 01 MA1[51:0] / MA1[47:24] register
A 10 A[23:0] register
B 11 B[23:0] register
· mgx
Mnemonic Encoding Description
Y0 00 Y0[23:0] register
Y1 01 Y1[23:0] register
X0 10 X0[23:0] register
X1 11 X1[23:0]
· mg
Mnemonic Encoding Description
MA0(H) 00000 MA0[51:0] / MA0[47:24] register
MA0L 00001 MA0[23:0] register
MA1(H) 00010 MA1[51:0] / MA1[47:24] register
MA1L 00011 MA1[23:0] register
MA0SR 00100 arithmetic right one bit shifted MA0[47:24] register
MA0SL 00101 arithmetic left one bit shifted MA0[47:24] register
MA1SR 00110 arithmetic right one bit shifted MA1[47:24] register
MA1SL 00111 arithmetic left one bit shifted MA1[47:24] register
RP0 01000 current bank RP0[15:0] register
RP1 01001 current bank RP1[15:0] register
RP2 01010 current bank RP2[15:0] register
RP3 01011 current bank RP3[15:0] register
RPD0 01100 RPD0[15:0] register
RPD1 01101 RPD1[15:0] register
MC0 01110 MC0[15:0] register
MC1 01111 MC1[15:0] register
SD0 01000 current bank SD0[15:0]/SD0E register
SD1 01001 current bank SD1[15:0] register
SD2 01010 current bank SD2[15:0] register
SD3 01011 current bank SD3[15:0]/SD3E register
SA 01100 SA[6:0] register
SI 01101 SI[23:0] register
SG 01110 SG[23:0] register
SR 01111 SR[23:0] register
P(H) 11000 P[47:24] register
PL 11001 P[23:0] register
MA0RN 11010 rounded MA0[47:24] register
MA1RN 11011 rounded MA1[47:24] register
MSR0 11100 MSR0[15:0] register
MSR1 11101 MSR1[15:0] register
MSR2 11110 MSR2[15:0] register
PRN 11111 rounded P[47:24] register
NOTE: Grayed Field: read only · mci
Mnemonic Encoding Description
MC0 0 MC0[15:0] register
MC1 1 MC1[15:0] register
· srg
Mnemonic Encoding Description
SA 00 SA[6:0] register
SI 01 SI[23:0] register
SG 10 SG[23:0] register
SR 11 SR[23:0] register
· asr
Mnemonic Encoding Description
A 00 A[23:0] register
B 01 B[23:0] register
SI 10 SI[23:0] register
SR 11 SR[23:0] register
· asa
Mnemonic Encoding Description
A 00 A[6:0] register
B 01 B[6:0] register
SA 10 SA[6:0] register
11 reserve
· bs
| Mnemonic | Encoding | Description |
|---|---|---|
| BK0 | 0000 | MSR2[12] |
| BK1 | 0001 | MSR2[13] |
| BK2 | 0010 | MSR2[14] |
| BK3 | 0011 | MSR2[15] |
| ME0 | 0100 | MSR0[12] |
| ME1 | 0101 | MSR0[13] |
| ME2 | 0110 | MSR0[14] |
| ME3 | 0111 | MSR0[15] |
| OPM | 1000 | MSR1[3] |
| OPMA | 1001 | MSR1[7] |
| OP | 1010 | MSR0[9] |
| USM | 1011 | MSR1[4] |
| MV | 1100 | MSR1[2] |
| XSD | 1101 | MSR0[10] |
| PSH1 | 1110 | MSR1[5] |
| NQ | 1111 | MSR1[6] |
· ereg
Mnemonic Encoding Description
AH 0000 A[23:16] register
BH 0001 B[23:16] register
CH 0010 C[23:16] register
DH 0011 D[23:16] register
A 0100 A[15:0] register
B 0101 B[15:0] register
C 0110 C[15:0] register
D 0111 D[15:0] register
SA 1000 SA[6:0] register
SI 1001 SI[15:0] register
SG 1010 SG[15:0] register
SR 1011 SR[15:0] register
1100 reserved
1101 reserved
1110 reserve
· ns
Mnemonic Encoding Description
S0 00 SDi[3:0] register
S1 01 SDi[7:4] register
D0 10 SDi[11:8] register
D1 11 SDi[15:12] register
· emod0
Mnemonic Encoding Description
ELD 00 Load
EADD 01 Add
ESUB 10 Subtract
ECP 11 Compare
· Pi
Mnemonic Encoding Description
P(H) 0 P[47:24] register
PL 1 P[23:0] register
· cct
Mnemonic Encoding Description
Z 0000 Z=1
NZ 0001 Z=0
NEG 0010 N=1
POS 0011 N=0
C 0100 C=1
NC 0101 C=0
V 0110 V=1
NV 0111 V=0
GT 1000 N = 0 and Z = 0
LE 1001 N = 1 or Z = 1
VM0 1010 VM0 = 1
VM1 1011 VM1 = 1
VS 1100 VS = 1
1101 reserved
MV 1110 MV = 1
1111 reserved
· emod1
Mnemonic Encoding Description
ESRA(T) 0000 Arithmetic shift right 1-bit
ESLA(T) 0001 Arithmetic shift left 1-bit
ESRA8(T) 0010 Arithmetic shift right 8-bit
ESLA8(T) 0011 Arithmetic shift left 8-bit
ESRC(T) 0100 Arithmetic shift right 1-bit with Carry
ESLC(T) 0101 Arithmetic shift left 1-bit with Carry
EINCC(T) 0110 Increment with Carry
EDECC(T) 0111 Decrement with Carry
ENEG(T) 1000 Negate
EABS(T) 1001 Absolute
EFS16(T) 1010 Force to Sign bit 23bit 8 by bit 7
EFZ16(T) 1011 Force to Zero bit 23bit 8
EFS8(T) 1100 Force to Sign bit 23bit 16 by bit 15
EFZ8(T) 1101 Force to Zero bit 23bit 16
EEXP(T) 1110 Exponent detection
EEXPC(T) 1111 Exponent detection with Carry
NOTE: “T” suffix means that instruction is executed when T flag is set. · emod2
Mnemonic Encoding Description
ESRA 0000 Arithmetic shift right 1-bit
ESLA 0001 Arithmetic shift left 1-bit
ERND 0010 Rounding
ECR 0011 Clear
ESAT 0100 Saturate
ERESR 0101 Restore Remainder
0110 reserved
0111 reserved
ELD MAi,MAi' 1000 Load from MAi' to MAi
1001 reserved
EADD MAi,P 1010 Add MAi and P
ESUB MAi,P 1011 Subtract P from MAi
EADD MAi,PSH 1100 Add MAi and 24-bit right shifted P
ESUB MAi,PSH 1101 Subtract 24-bit right shifted P from MAi
EDIVQ 1110 Division Step
1111 reserve